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mos integrated circuit m m m m pd16633b 312 output tft-lcd sorce driver (compatible with 64 gray scales) 1998 ? document no. s13214ej2v0ds00 (2nd edition) date published july 1998 n cp(k) printed in japan data sheet the m pd16633b is a source driver for tft-lcds capable of dealing with displays with 64 gray scales. data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values g -corrected by an internal d/a converter and 5-by-2 external power modules. because the output dynamic range is as large as 9.8 v p-p , level inversion operation of the lcds common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion when mounted on a single side, this source driver is equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polarity. assuring a maximum clock frequency of 45 mhz when driving at 3.0 v, this driver is applicable to xga-standard tft-lcd panels. features ? capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a d/a converter ? output dynamic range 9.8 v p-p min. (@v dd2 = 10.0 v) ? cmos level input ? input of 6 bits (gradation data) by 6 dots ? high-speed data transfer: fmax. = 45 mhz (internal data transfer speed when operating at 3.0 v) ? 312 outputs ? apply for only dot inversion ? display data inversion function (pol2 terminal.) ? single bank arrangement is possible (loaded with slim tcp) ordering information part number package m pd16633bn- tcp (tab package) the tcps external shape is customized. to order your tcps external shape, please contact a nec salesperson.
2 m m m m pd16633b 1. block diagram 50-bit bidirectional shift register c 1 c 2 c 51 c 52 sthl v dd1 v ss1 clk stb data register latch pol level shifter v dd2 d/a converter v 0 -v 9 voltage follower output v ss2 s 1 s 2 s 3 s 312 sthr r/l d 00 - 05 d 10 - 15 d 20 - 25 d 30 - 35 d 40 - 45 d 50 - 55 pol2 2. relationship between output circuit and d/a converter 6-bit d/a converter multi- plexer v 0 v 4 v 5 v 9 5 5 s 1 s 2 s 311 s 312 pol
3 m m m m pd16633b 3. pin configuration ( m m m m pd16633bn- ) (copper plated surface) v ss2 v dd2 v ss1 r/l pol stb d 55 d 54 d 53 d 52 d 51 d 50 d 45 d 44 d 43 d 42 d 41 d 40 d 35 d 34 d 33 d 32 d 31 sthl v 9 v 8 v 7 v 6 v 5 v 4 v 3 v 2 v 1 v 0 clk sthr d 30 d 25 d 24 d 23 d 22 d 21 d 20 d 15 d 14 d 13 d 12 d 11 d 10 d 05 d 04 d 03 d 02 d 01 d 00 pol2 test v dd1 v dd2 v ss2 s 312 s 311 s 310 s 309 s 4 s 3 s 2 s 1 caution this figure does not specify the tcp package.
4 m m m m pd16633b 4. pin functions pin symbol pin name description s 1 to s 312 driver output the d/a converted 64-gray-scale analog voltage is output. d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 d 50 to d 55 display data input the display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). d x0 : lsb, d x5 : msb r/l shift direction control input these refer to the start pulse input/output pins when driver ics are connected in cascade. the shift directions of the shift registers are as follows. r/l = h : sthr input, s 1 ? s 312 , sthl output r/l = l : sthl input, s 312 ? s 1 , sthr output sthr right shift start pulse input/output r/l = h : becomes the start pulse input pin. r/l = l : becomes the start pulse output pin. sthl left shift start pulse input/output r/l = h : becomes the start pulse output pin. r/l = l : becomes the start pulse input pin. clk shift clock input refers to the shift registers shift clock input. the display data is incorporated into the data register at the rising edge. at the rising edge of the 52nd clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. the initial-level drivers 52nd clock becomes valid as the next-level drivers start pulse is input. if 54th clock pulses are input after input of the start pulse, input of display data is halted automatically. the contents of the shift register are cleared at the stbs rising edge. stb latch input the contents of the data register are transferred to the latch circuit at the rising edge. and, at the falling edge, the gray scale voltage is supplied to the driver. it is necessary to ensure input of one pulse per horizontal period. pol polarity input pol = l ; the s 2nC1 output uses v 0 to v 4 as the reference supply; the s 2n output uses v 5 to v 9 as the reference supply. pol = h; the s 2nC1 output uses v 5 to v 9 as the reference supply; the s 2n output uses v 0 to v 4 as the reference supply. pol2 data inversion pol2 = h : display data is inverted. pol2 = l : display data is not inverted. v 0 to v 9 g -corrected power supplies input the g -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 > v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 test test pin test = h or open: standard mode test = l: test mode please input h level. v dd1 logic power supply 3.3 v 0.3 v v dd2 driver power supply 10.0 v to 13.5 v v ss1 logic ground grounding v ss2 driver ground grounding
5 m m m m pd16633b cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 9 in that order. reverse this sequence to shut down. (simultaneous power application to v dd2 and v 0 to v 9 is possible.) 2. to stabilize the supply voltage, please be sure to insert a 0.47 m m m m f bypass capacitor between v dd1 -v ss1 and v dd2 -v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 m m m m f is also advised between the g g g g -corrected power supply terminals (v 0 , v 1 , v 2 , , v 9 ) and v ss2 .
6 m m m m pd16633b 5. relationship between input data and output voltage value this product incorporates a 6-bit d/a converter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the lcds counter electrode (common electrode) voltage. the d/a converter consists of ladder resistors and switches. the ladder resistors r 0 to r 62 are so designed that the ratios between the lcd panels g -corrected voltages and v 0 to v 63 and v 0 to v 63 are roughly equal; and their respective resistance values are as shown on page 9. among the 5-by-2 g -corrected voltages, input gray scale voltages of the same polarity with respect to the common voltage, for the respective five g -corrected voltages of v 0 to v 4 and v 5 to v 9 . figure 1 shows the relationship between the driving voltages such as liquid-crystal driving voltages v dd2 and v ss2 , common electrode potential v com , and g -corrected voltages v 0 to v 9 and the input data. be sure to maintain the voltage relationships of v dd2 > v 0 > v 1 > v 2 > v 3 > v 4 > v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 . figures 2-1 and 2-2 show the relationship between the input data and the output data. table 1 shows the resistance values of the resistor strings. this driver ic is designed for single-sided mounting. therefore, please do not use it for g -corrected power supply level inversion in double-sided mounting. because the current flowing through ladder resistors r 0 to r 62 is small, its use for double-sided mounting impairs the ics stable operation when the level of the g -corrected power supply terminal is inverted thus causing display failures. figure 1. relationship between input data and output voltage 3f 38 30 28 20 18 10 08 00 input data (hex) (pol2 = l) 40 (invalid) 0.1 v v 9 v ss2 0.1 v v 0 v dd2 v 1 v 2 v 3 v 4 v com v 5 v 6 v 7 v 8
7 m m m m pd16633b figure 2-1. relationship between input data and output voltage: v dd2 > v 0 > v 1 > v 2 > v 3 > v 4 > v 5 data d x5 d x4 d x3 d x2 d x1 d x0 output voltage 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 0 v 1 + (v 0 C v 1 ) 4500/5300 v 1 + (v 0 C v 1 ) 3700/5300 v 1 + (v 0 C v 1 ) 2900/5300 v 1 + (v 0 C v 1 ) 2200/5300 v 1 + (v 0 C v 1 ) 1500/5300 v 1 + (v 0 C v 1 ) 900/5300 v 1 + (v 0 C v 1 ) 400/5300 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 8 v 9 v 10 v 11 v 12 v 13 v 14 v 15 v 1 v 2 + (v 1 C v 2 ) 3600/4000 v 2 + (v 1 C v 2 ) 3300/4000 v 2 + (v 1 C v 2 ) 3000/4000 v 2 + (v 1 C v 2 ) 2700/4000 v 2 + (v 1 C v 2 ) 2400/4000 v 2 + (v 1 C v 2 ) 2200/4000 v 2 + (v 1 C v 2 ) 2000/4000 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 16 v 17 v 18 v 19 v 20 v 21 v 22 v 23 v 2 + (v 1 C v 2 ) 1800/4000 v 2 + (v 1 C v 2 ) 1600/4000 v 2 + (v 1 C v 2 ) 1400/4000 v 2 + (v 1 C v 2 ) 1300/4000 v 2 + (v 1 C v 2 ) 1200/4000 v 2 + (v 1 C v 2 ) 1100/4000 v 2 + (v 1 C v 2 ) 1000/4000 v 2 + (v 1 C v 2 ) 900/4000 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1f h 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 24 v 25 v 26 v 27 v 28 v 29 v 30 v 31 v 2 + (v 1 C v 2 ) 800/4000 v 2 + (v 1 C v 2 ) 700/4000 v 2 + (v 1 C v 2 ) 600/4000 v 2 + (v 1 C v 2 ) 500/4000 v 2 + (v 1 C v 2 ) 400/4000 v 2 + (v 1 C v 2 ) 300/4000 v 2 + (v 1 C v 2 ) 200/4000 v 2 + (v 1 C v 2 ) 100/4000 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 32 v 33 v 34 v 35 v 36 v 37 v 38 v 39 v 2 v 3 + (v 2 C v 3 ) 2600/2700 v 3 + (v 2 C v 3 ) 2500/2700 v 3 + (v 2 C v 3 ) 2400/2700 v 3 + (v 2 C v 3 ) 2300/2700 v 3 + (v 2 C v 3 ) 2200/2700 v 3 + (v 2 C v 3 ) 2100/2700 v 3 + (v 2 C v 3 ) 2000/2700 28 h 29 h 2a h 2b h 2c h 2d h 2e h 2f h 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 40 v 41 v 42 v 43 v 44 v 45 v 46 v 47 v 3 + (v 2 C v 3 ) 1900/2700 v 3 + (v 2 C v 3 ) 1800/2700 v 3 + (v 2 C v 3 ) 1700/2700 v 3 + (v 2 C v 3 ) 1600/2700 v 3 + (v 2 C v 3 ) 1500/2700 v 3 + (v 2 C v 3 ) 1400/2700 v 3 + (v 2 C v 3 ) 1300/2700 v 3 + (v 2 C v 3 ) 1200/2700 30 h 31 h 32 h 33 h 34 h 35 h 36 h 37 h 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 48 v 49 v 50 v 51 v 52 v 53 v 54 v 55 v 3 + (v 2 C v 3 ) 1100/2700 v 3 + (v 2 C v 3 ) 1000/2700 v 3 + (v 2 C v 3 ) 900/2700 v 3 + (v 2 C v 3 ) 800/2700 v 3 + (v 2 C v 3 ) 700/2700 v 3 + (v 2 C v 3 ) 600/2700 v 3 + (v 2 C v 3 ) 400/2700 v 3 + (v 2 C v 3 ) 200/2700 v 1 v 2 v 3 v 55 v 56 v 57 v 0 v 3 r 0 r 1 r 2 r 3 r 55 r 56 r 57 r 54 v 31 r 30 r 31 v 32 v 33 r 32 r 33 v 2 v 58 r 59 v 59 r 58 v 60 r 60 v 61 r 62 v 62 r 61 v 4 v 5 v 6 r 4 r 5 r 6 v 7 r 7 v 8 v 9 r 8 r 9 v 0 v 1 v 5 r 4-5 v 63 9 k w v 4 v 63 38 h 39 h 3a h 3b h 3c h 3d h 3e h 3f h 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 56 v 57 v 58 v 59 v 60 v 61 v 62 v 63 v 3 v 4 + (v 3 C v 4 ) 2300/2500 v 4 + (v 3 C v 4 ) 2100/2500 v 4 + (v 3 C v 4 ) 1800/2500 v 4 + (v 3 C v 4 ) 1500/2500 v 4 + (v 3 C v 4 ) 1200/2500 v 4 + (v 3 C v 4 ) 800/2500 v 4 caution between v 4 and v 5 terminal is connected by using the resistor (9 k w w w w ) in the chip.
8 m m m m pd16633b figure 2-2. relationship between input data and output voltage: v 4 > v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 data d x5 d x4 d x3 d x2 d x1 d x0 output voltage 00 h 01 h 02 h 03 h 04 h 05 h 06 h 07 h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 0 v 1 v 2 v 3 v 4 v 5 v 6 v 7 v 9 v 9 + (v 8 C v 9 ) 800/5300 v 9 + (v 8 C v 9 ) 1600/5300 v 9 + (v 8 C v 9 ) 2400/5300 v 9 + (v 8 C v 9 ) 3100/5300 v 9 + (v 8 C v 9 ) 3800/5300 v 9 + (v 8 C v 9 ) 4400/5300 v 9 + (v 8 C v 9 ) 4900/5300 08 h 09 h 0a h 0b h 0c h 0d h 0e h 0f h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 8 v 9 v 10 v 11 v 12 v 13 v 14 v 15 v 8 v 8 + (v 7 C v 8 ) 400/4000 v 8 + (v 7 C v 8 ) 700/4000 v 8 + (v 7 C v 8 ) 1000/4000 v 8 + (v 7 C v 8 ) 1300/4000 v 8 + (v 7 C v 8 ) 1600/4000 v 8 + (v 7 C v 8 ) 1800/4000 v 8 + (v 7 C v 8 ) 2000/4000 10 h 11 h 12 h 13 h 14 h 15 h 16 h 17 h 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 16 v 17 v 18 v 19 v 20 v 21 v 22 v 23 v 8 + (v 7 C v 8 ) 2200/4000 v 8 + (v 7 C v 8 ) 2400/4000 v 8 + (v 7 C v 8 ) 2600/4000 v 8 + (v 7 C v 8 ) 2700/4000 v 8 + (v 7 C v 8 ) 2800/4000 v 8 + (v 7 C v 8 ) 2900/4000 v 8 + (v 7 C v 8 ) 3000/4000 v 8 + (v 7 C v 8 ) 3100/4000 18 h 19 h 1a h 1b h 1c h 1d h 1e h 1f h 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 24 v 25 v 26 v 27 v 28 v 29 v 30 v 31 v 8 + (v 7 C v 8 ) 3200/4000 v 8 + (v 7 C v 8 ) 3300/4000 v 8 + (v 7 C v 8 ) 3400/4000 v 8 + (v 7 C v 8 ) 3500/4000 v 8 + (v 7 C v 8 ) 3600/4000 v 8 + (v 7 C v 8 ) 3700/4000 v 8 + (v 7 C v 8 ) 3800/4000 v 8 + (v 7 C v 8 ) 3900/4000 20 h 21 h 22 h 23 h 24 h 25 h 26 h 27 h 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 32 v 33 v 34 v 35 v 36 v 37 v 38 v 39 v 7 v 7 + (v 6 C v 7 ) 100/2700 v 7 + (v 6 C v 7 ) 200/2700 v 7 + (v 6 C v 7 ) 300/2700 v 7 + (v 6 C v 7 ) 400/2700 v 7 + (v 6 C v 7 ) 500/2700 v 7 + (v 6 C v 7 ) 600/2700 v 7 + (v 6 C v 7 ) 700/2700 28 h 29 h 2a h 2b h 2c h 2d h 2e h 2f h 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 40 v 41 v 42 v 43 v 44 v 45 v 46 v 47 v 7 + (v 6 C v 7 ) 800/2700 v 7 + (v 6 C v 7 ) 900/2700 v 7 + (v 6 C v 7 ) 1000/2700 v 7 + (v 6 C v 7 ) 1100/2700 v 7 + (v 6 C v 7 ) 1200/2700 v 7 + (v 6 C v 7 ) 1300/2700 v 7 + (v 6 C v 7 ) 1400/2700 v 7 + (v 6 C v 7 ) 1500/2700 30 h 31 h 32 h 33 h 34 h 35 h 36 h 37 h 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 48 v 49 v 50 v 51 v 52 v 53 v 54 v 55 v 7 + (v 6 C v 7 ) 1600/2700 v 7 + (v 6 C v 7 ) 1700/2700 v 7 + (v 6 C v 7 ) 1800/2700 v 7 + (v 6 C v 7 ) 1900/2700 v 7 + (v 6 C v 7 ) 2000/2700 v 7 + (v 6 C v 7 ) 2100/2700 v 7 + (v 6 C v 7 ) 2300/2700 v 7 + (v 6 C v 7 ) 2500/2700 v 63 v 62 v 61 v 33 v 32 v 31 v 2 v 4 v 7 v 9 r 4-5 r 62 r 61 r 60 r 32 r 31 r 30 r 2 r 0 r 33 v 57 r 56 v 56 v 55 r 55 r 54 v 6 v 1 r 1 v 0 v 4 " r 4 v 3 r 3 v 6 r 6 v 5 r 5 v 7 r 7 v 9 r 9 v 8 r 8 v 8 v 60 v 59 v 58 r 59 r 58 v 63 v 5 r 57 9 k w 38 h 39 h 3a h 3b h 3c h 3d h 3e h 3f h 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 v 56 v 57 v 58 v 59 v 60 v 61 v 62 v 63 v 6 v 6 + (v 5 C v 6 ) 200/2500 v 6 + (v 5 C v 6 ) 400/2500 v 6 + (v 5 C v 6 ) 700/2500 v 6 + (v 5 C v 6 ) 1000/2500 v 6 + (v 5 C v 6 ) 1300/2500 v 6 + (v 5 C v 6 ) 1700/2500 v 5 caution between v 4 and v 5 terminal is connected by using the resistor (9 k w w w w ) in the chip.
9 m m m m pd16633b ladder resistance value (r 0 to r 62 ): reference value table 1. resistance values of the resistor strings resistor name resistance value ( w ) resistor name resistance value ( w ) r 0 r 1 r 2 r 3 r 4 r 5 r 6 r 7 r 8 r 9 r 10 r 11 r 12 r 13 r 14 r 15 r 16 r 17 r 18 r 19 r 20 r 21 r 22 r 23 r 24 r 25 r 26 r 27 r 28 r 29 r 30 r 31 800 800 800 700 700 600 500 400 400 300 300 300 300 200 200 200 200 200 100 100 100 100 100 100 100 100 100 100 100 100 100 100 r 32 r 33 r 34 r 35 r 36 r 37 r 38 r 39 r 40 r 41 r 42 r 43 r 44 r 45 r 46 r 47 r 48 r 49 r 50 r 51 r 52 r 53 r 54 r 55 r 56 r 57 r 58 r 59 r 60 r 61 r 62 total 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 200 200 200 200 200 300 300 300 400 800 14500 v 0 , v 9 v 1 , v 8 v 2 , v 7 v 4 , v 5 v 3 , v 6 v 2 , v 7
10 m m m m pd16633b 6. relationship between input data and output pin data format : 6 bits 2 rgbs (6 dots) input width : 36 bits (2-pixel data) r/l = h (right shift) output s 1 s 2 s 3 s 4 s 311 s 312 data d 00 -d 05 d 10 -d 15 d 20 -d 25 d 30 -d 35 d 40 -d 45 d 50 -d 55 r/l = l (left shift) output s 1 s 2 s 3 s 4 s 311 s 312 data d 00 -d 05 d 10 -d 15 d 20 -d 25 d 30 -d 35 d 40 -d 45 d 50 -d 55 s 2nC1 (odd output), s 2n (even output) n = 1, 2, , 156 pol s 2nC1 s 2n lv 0 to v 4 v 5 to v 9 hv 5 to v 9 v 0 to v 4 7. relationship between stb, pol, and output waveform stb pol s 2n-1 s 2n selected voltage of v 0 to v 4 selected voltage of v 5 to v 9 selected voltage of v 0 to v 4 selected voltage of v 5 to v 9 selected voltage of v 0 to v 4 selected voltage of v 5 to v 9 hi-z hi-z hi-z
11 m m m m pd16633b 8. cautions about frame inversion in the case of dot inversion, n frame last line and (n+1) frame first line is the same polarity. when write the same polarity twice, there are two cases as follows. (1) last line output in n frame > first line output in (n+1) frame ? possible to write (2) last line output in n frame < first line output in (n+1) frame ? not possible to write m pd16633b has charge buffer and discharge buffer, so need to inversion polarity and write in the case of both ways. stb pol s 2n n frame last line (n+1) frame first line (n+1) frame second line discharge buffer charge buffer v com hi-z hi-z hi-z stb pol s 2n n frame last line (n+1) frame first line (n+1) frame second line v com hi-z hi-z hi-z hi-z vertical intervals vertical intervals
12 m m m m pd16633b 9. electric specification absolute maximum ratings (t a = 25c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 C0.5 to +6.5 v driver part supply voltage v dd2 C0.5 to +15.0 v logic part input voltage v i1 C0.5 to v dd1 + 0.5 v driver part input voltage v i2 C0.5 to v dd2 + 0.5 v logic part output voltage v o1 C0.5 to v dd1 + 0.5 v driver part output voltage v o2 C0.5 to v dd2 + 0.5 v operating temperature range t a C10 to +75 c storage temperature range t stg C55 to +125 c recommended operating condition (t a = C10 to +75c, v ss1 = v ss2 = 0 v) parameter symbol min. typ. max. unit logic part supply voltage v dd1 3.0 3.3 3.6 v driver part supply voltage v dd2 10.0 10.5 13.5 v high-level input voltage v ih 0.7v dd1 v dd1 v low-level input voltage v il v ss1 0.3v dd1 v g -corrected voltage v 0 to v 9 v ss2 + 0.05 v dd2 C 0.05 v driver part output voltage v o v ss2 + 0.1 v dd2 C 0.1 v maximum clock frequency f max. 45 mhz electrical specifications (t a = C10 to +75c, v dd1 = 3.3 v 0.3 v, v dd2 = 10.5 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit input leak current i il 1.0 m a high-level output voltage v oh sthr (sthl), i oh = 0 ma v dd1 C 0.1 v low-level output voltage v ol sthr (sthl), i ol = 0 ma 0.1 v g -corrected supply current i g v 0 -v 9 = 10 v v 0 , v 9 0.3 0.5 ma v voh v x = 9 v, v out = 3 v note C0.6 C0.3 ma driver output current v vol v x = 3 v, v out = 9 v note 0.3 0.6 ma note v x refers to the output voltage of analog output pins s 1 to s 312 . v out refers to the voltage applied to analog output pins s 1 to s 312 .
13 m m m m pd16633b electrical specifications (t a = C10 to +75c, v dd1 = 3.3 v 0.3 v, v dd2 = 10.5 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit output voltage deviation note 1 d v o input data 5 20 mv average output voltage variation note 2 d v av input data 10 mv output voltage range v o input data 0.1 v dd2 C 0.1 v logic part dynamic current consumption i dd1 v dd1 , no loads 1.6 10.0 ma driver part dynamic current consumption 1 notes 3, 4 i dd21 v dd2 = 10.5 v 0.5 v, no loads 4.4 8.0 ma driver part dynamic current consumption 1 notes 3, 4 i dd22 v dd2 = 13.5 v 0.5 v, no loads 6.4 10.0 ma notes 1. the output voltage deviation refers to the voltage difference between adjoining output pins when the display data is the same (within the chip). 2. the average output voltage variation refers to the average output voltage difference between chips. the average output voltage refers to the average voltage between chips when the display data is the same. 3. the stb cycle is defined to be 20 m s at f clk = 40 mhz. the typ. values refer to an all black or all white input pattern. the max. value refers to the measured values in the dot checkerboard input pattern. 4. refers to the current consumption per driver when cascades are connected under the assumption of xga single-sided mounting (10 units). switching characteristics (t a = C10 to +75c, v dd1 = 3.3 v 0.3 v, v dd2 = 10.5 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit start pulse delay time t plh1 c l = 25 pf 10 15 ns driver output delay time 1 t plh2 c l = 50 pf, r l = 50 k w 6.6 11 m s driver output delay time 2 t plh3 c l = 50 pf, r l = 50 k w 10 17 m s driver output delay time 3 t phl2 c l = 50 pf, r l = 50 k w 6.4 11 m s driver output delay time 4 t phl3 c l = 50 pf, r l = 50 k w 9.1 17 m s input capacitance 1 c i1 sthr (sthl) excluded, t a = 25c 6.4 15 pf input capacitance 2 c i2 sthr (sthl), t a = 25c 6.3 15 pf
14 m m m m pd16633b timing requirement (t a = C10 to +75c, v dd1 = 3.3 v 0.3 v, v ss1 = v ss2 = 0 v, t r = t f = 8.0 ns) parameter symbol condition min. typ. max. unit clock pulse width pw clk 22 ns clock pulse low period pw clk(h) 6ns clock pulse high period pw clk(l) 6ns data setup time t setup1 6ns data hold time t hold1 6ns start pulse setup time t setup2 6ns start pulse hold time t hold2 6ns pol2 setup time t setup3 6ns pol2 hold time t hold3 6ns start pulse low period t spl 5ns stb pulse width pw stb 0.5 m s data invalid period t inv 1clk last data timing t ldt 2clk clk-stb time t clk-stb clk - ? stb 5ns stb-clk time t stb-clk stb ? clk 5ns time between stb and start pulse t stb-sth stb ? sthr (l) - 50 ns pol-stb time t pol-stb pol - or ? stb - C5 ns stb-pol time t stb-pol stb ? pol or - 5ns
15 m m m m pd16633b 10. switching characteristics waveform (r/l = h) unless otherwise specified, the input level is defined to be v ilh = 0.5v dd1 sthr (1st dr.) clk v dd1 v ss1 d n0 to d n5 pol2 sthl (1st dr.) stb pol 1 2 3 52 53 54 513 514 1 2 t spl t setup2 t hold2 invalid d 1 to d 6 d 7 to d 12 d 301 to d 306 d 307 to d 312 d 313 to d 318 d 3067 to d 3072 invalid d 1 to d 3 d 4 to d 6 t setup1 t hold1 invalid invalid t setup3 t hold3 t plh1 t inv t ldt pw stb t clk-stb t stb-clk t phl3 t phl2 t plh2 t plh3 hi-z target voltage 0.1 v dd2 t pol-stb t stb-pol v out pw clk (l) pw clk pw clk (h) t stb-sth t r t f 90 % 10 % v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 6 bit accuracy
16 m m m m pd16633b 11. recommended mounting conditions when mounting this product, please make sure that the following recommended conditions are satisfied. for packaging methods and conditions other than those recommended below, please contact nec sales personnel. mounting condition mounting method condition soldering heating tool 300 to 350c, heating for 2 to 3 sec; pressure 100 g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100c; pressure 3 to 8 kg/cm 2 ; time 3 to 5 sec. real bonding 165 to 180c; pressure 25 to 45 kg/cm 2 , time 30 to 40 secs. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd) caution to find out the detailed conditions for packaging the acf part, please contact the acf manufacturing company. be sure to avoid using two or more packaging methods at a time. reference nec semiconductor device reliability/quality control system (c10983e) quality grades to necs semiconductor devices (c11531e)
17 m m m m pd16633b [memo]
18 m m m m pd16633b [memo]
19 m m m m pd16633b [memo]
m m m m pd16633b no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96. 5

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